Surface quality and contamination on Si wafer surfaces sliced using wire-EDM

[+] Author and Article Information
Kamlesh Joshi

Powai Mumbai, Maharashtra 400076 India joshi.kamleshmt@gmail.com

Pradeep Padhamnath

Machine Tools Lab (S3 Bay) Mumbai, Maharastra 400076 India pradeep2603@gmail.com

Upendra Bhandarkar

Department of Mechanical Engineering Indian Institute of Technology Bombay Mumbai, Maharashtra 400076 India bhandarkar@iitb.ac.in

Suhas S. Joshi

Mechanical Engineering Department Mumbai, 400076, India ssjoshi@iitb.ac.in

1Corresponding author.

Contributed by the Materials Division of ASME for publication in the Journal of Engineering Materials and Technology. Manuscript received January 5, 2019; final manuscript received July 26, 2019; published online xx xx, xxxx. Assoc. Editor: Pradeep Sharma.

ASME doi:10.1115/1.4044374 History: Received January 05, 2019; Accepted July 26, 2019


In the past, studies on wire-EDM of Si wafers have often focussed on the effect of energy related parameters on various wafer characteristics. However, comprehensive treatment on analysing the effect of non-energy parameters of the Si wafer slicing process is not available thus far. This work, therefore, presents an extensive experimental work considering parameters like wire tension (WT), wire feed rate (WF) and dielectric flushing pressure (WaP) on crucial wafer characteristics such as wafer thickness and its uniformity, thermal damage, wire material contamination on wafer surfaces and surface quality. A total of 72 experiments were performed at low and high servo voltage (SV) conditions. The sliced wafers were characterised by SEM, EDAX and ICP-AES techniques. Ultra-thin wafers with uniform thickness ~107 µm were sliced at high SV conditions, while a lower thermal damage (~10 µm) with low wire contamination was observed during low SV conditions. The percentage of contamination was further found to decrease with an increase in WT, WF and WaP during low SV conditions. The wafer surface etching showed diffusion of contaminates like Cu/Zn up to a depth of 25-30 µm. The wafer surface roughness in the middle section has always been observed to be poor due to short circuiting and arcing within that zone.

Copyright © 2019 by ASME
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