The reliability of solder bumped flip chips on organic coated copper (OCC) printed circuit board (PCB) has been studied by shock and vibration tests and a mathematical analysis. Two different chip sizes (7 mm and 14 mm on a side) have been studied, and the larger chips have many internal solder bumps. For the in-plane and out-of-plane and out-of-plane shock tests, the chips were assembled with and without underfill encapsulants. However, for the out-of-plane vibration tests all the chips were underfilled with epoxy.
Issue Section:
Technical Briefs
1.
Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York, NY, 1996.
2.
Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, NY, 1995.
3.
Lau, J. H., Chip On Board Technologies for Multichip Modules, Van Nostrand Reinhold, Feb. 1994.
4.
Lau, J. H., Handbook of Fine Pitch Surface Mount Technology, Van Nostrand Reinhold, New York, NY, 1993.
5.
Lau, J. H., Handbook of Tape Automated Bonding, Van Nostrand Reinhold, New York, NY, 1992.
6.
Totta, P., “Flip Chip Solder Terminals,” Proceedings of the IEEE Electronic Components Conference, pp. 275–284, 1971.
7.
Goldmann, L. S., “Geometric Optimization of Controlled Collapse Interconnections,” IBM Journal of Research and Development, May 1969, pp. 251–265.
8.
Goldmann, L. S., “Optimizing Cycle Fatigue Life of Controlled Collapse Chip Joints,” Proceedings of the 19th IEEE Electronic Components and Technology Conference, 1969, pp. 404–423.
9.
Miller, L. F., “Controlled Collapse Reflow Chip Joining,” IBM Journal of Research and Development, May 1969, pp. 239–250.
10.
Miller, L. F., “A Survey of Chip Joining Techniques,” Proceedings of the 19th IEEE Electronic Components and Technology Conference, 1969, pp. 60–76.
11.
Miller, L. F., “Joining Semiconductor Devices with Ductile Pads,” Proceedings of ISHM, pp. 333–342, 1968.
12.
Tsukada, Y., Maeda, Y., and Yamanaka, K., “A Novel Solution for MCM-L Utilizing Surface Laminar Circuit and Flip Chip Attach Technology,” Proceedings of the 2nd International Conference and Exhibition on Multichip Modules, April 1993, pp. 252–259.
13.
Tsukada, Y., Tsuchida, S., and Mashimoto, Y., “Surface Laminar Circuit Packaging,” Proceedings of the 42nd IEEE Electronic Components and Technology Conference, May 1992, pp. 22–27.
14.
Tsukada, Y., “Solder Bumped Flip Chip Attach on SLC Board and Multichip Module,” Chip On Board Technologies for Multichip Modules, Lau, J. H., ed., Van Nostrand Reinhold, New York, 1994, pp. 410–443.
15.
Rai, A., Dotta, Y., Tsukamoto, Fujiwara, T., Ishii, H., Nukii, T., and Matsui, H., “COB (Chip On Board) Technology: Flip Chip Bonding Onto Ceramic Substrates and PWB (Printed Wiring Boards),” ISHM Proceedings, 1990, pp. 474–481.
16.
Rai, A., Dotta, Y., Nukii, T., and Ohnishi, T., “Flip-Chip COB Technology on PWB,” Proceedings of IMC, June 1992, pp. 144–149.
17.
Steinberg, D. S., Vibration Analysis for Electronic Equipment, John Wiley and Sons, New York, N.Y., 1973.
18.
Steinberg, D. S., “Protecting PCBs From Shock,” Machine Design, March 1983, pp. 189–192.
19.
Markstein, H. W., “Designing Electronics for High Vibration and Shock,” Electronic Packaging and Production, April 1987, pp. 40–43.
20.
Markstein, H. W., “Design With Vibration in Electronics,” Electronic Packaging and Production, June 1989, pp. 30–34.
21.
Environmental Tests, Sections 759 and 760, Hewlett-Packard Company, 1986.
22.
Lau
J. H.
Powers
L.
Baker
J.
Rice
D.
Shaw
W.
Solder Joint Reliability of Fine Pitch Surface Mount Technology Assemblies
,” IEEE Transaction on Components, Hybrid, and Manufacturing Technology
, Vol. 13
, Sept. 1990
, pp. 534
–544
.23.
Lau
J. H.
Marcotte
T.
Severine
J.
Lee
A.
Erasmus
S.
Baker
T.
Moldaschel
J.
Sporer
M.
Burward-Hoy
G.
Solder Joint Reliability of Surface Mount Connectors
,” ASME JOURNAL OF ELECTRONIC PACKAGING
, Vol. 115
, June 1993
, pp. 180
–188
.
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